- Dec 26, 2012
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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- Dec 23, 2012
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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- Nov 14, 2012
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Siarhei Siamashka authored
incr - PLD prefetch hits the first bytes of cache lines wrap - PLD prefetch hist the last bytes of cache lines This can expose Raspberry Pi performance issues related to wrap cache linefills.
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- Apr 24, 2012
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
Now the compilers should have no chance to mess up latency measurement loops by adding unwanted memory accesses.
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Siarhei Siamashka authored
The compilers should be a bit less likely to spill variables to stack.
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- Oct 09, 2011
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Siarhei Siamashka authored
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Siarhei Siamashka authored
Checks how the processor can handle outstanding cache misses.
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- Sep 12, 2011
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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- Sep 10, 2011
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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- Sep 09, 2011
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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- Sep 08, 2011
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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Siarhei Siamashka authored
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