Just select a random offset in order to mitigate the unpredictability
of cache associativity effects when dealing with different physical
memory fragmentation (for PIPT caches). We are reporting the "best"
measured latency, some offsets may be better than the others.

/tmp/ccej9DYL.s:47: Rd and Rm should be different in mla (repeated)
/tmp/ccej9DYL.s:754: Rd and Rm should be different in mla (repeated)
/tmp/ccej9DYL.s:720: Error: bad immediate value for offset (5328)
/tmp/ccej9DYL.s:724: Error: bad immediate value for offset (5316)
/tmp/ccej9DYL.s:725: Error: bad immediate value for offset (5316)

https://github.com/ssvb/tinymembench/issues/1

incr - PLD prefetch hits the first bytes of cache lines
wrap - PLD prefetch hist the last bytes of cache lines

This can expose Raspberry Pi performance issues related to
wrap cache linefills.

Now the compilers should have no chance to mess up latency
measurement loops by adding unwanted memory accesses.

The compilers should be a bit less likely to spill variables to stack.

Checks how the processor can handle outstanding cache misses.